Memory is one type of integrated circuitry and may be used in electronic systems for storing data. Integrated memory is usually fabricated in one or more arrays of individual memory cells.
The memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.
One type of memory cell is phase change memory (PCM). Such memory utilizes phase change material as a programmable material. Example phase change materials that may be utilized in PCM are chalcogenide materials.
The phase change material reversibly transforms from one phase to another through application of appropriate stimulus. Each phase may be utilized as a memory state, and thus an individual PCM cell may have two selectable memory states that correspond to two inducible phases of the phase change material.
FIGS. 1 and 2 diagrammatically illustrate a couple of prior art memory structures. Specifically, FIGS. 1A and 1B illustrate a memory structure 2 utilizing a heater, and FIGS. 2A and 2B illustrate a memory structure 2a in a heaterless configuration.
The memory structure 2 of FIG. 1 is shown to comprise a heater plate 3 which is beneath and directly against a storage element 4 of phase change material (the phase change material may comprise, for example, chalcogenide material). The heater plate and the storage element are together comprised by a phase change memory cell 9, with the heater being utilized to induce a change in phase within the storage element (for instance, within chalcogenide) during programming of such memory cell.
The heater plate is over and directly against electrically conductive material 5 (which may be, for example, silicide), and the electrically conductive material 5 is over other materials 6 within a pedestal. The pedestal may include a select device (for instance, a bipolar transistor) which is coupled to the adjacent memory cell 9 to alleviate potential leakage problems.
A wordline 7 is beneath the memory cell, and a bitline 8 is above the memory cell. In operation, voltage differentials between the wordline and bitline are utilized for writing to, and reading from, the memory cell.
The heaterless memory structure 2a of FIG. 2 differs from the memory structure shown in FIG. 1 in that the cell 9 of FIG. 2 comprises the storage element 4 (for instance, chalcogenide) configured as a plate, and lacks the heater plate (i.e., the plate 3 of FIG. 1).
The memory cells 9 of FIGS. 1 and 2 may be incorporated into memory arrays. FIG. 3 shows a top view of an example prior art memory array 12. Wordlines 7a-d extend along the row directions of the array, and bitlines 8a-d extend along column directions of the array. Plates 10 (which may be either the heater plates of the FIG. 1 cell or chalcogenide plates of the FIG. 2 cell) are diagrammatically illustrated to be present at cross-points where wordlines and bitlines overlap. The plates would actually be over the wordlines and under the bitlines (as shown in the side views of FIGS. 1 and 2), and accordingly would not be visible in the top view of FIG. 3. However, the locations of the plates are shown in FIG. 3 in order to assist the reader in understanding the prior art pattern.
A difficulty that may be encountered during utilization of PCM is thermal cross-talk between adjacent memory cells. Specifically, the induction of a phase change within one memory cell may inadvertently trigger a change in a neighboring memory cell. The thermal crosstalk may cause a so-called “program-disturb” phenomena in which data is lost from a memory cell during programming of a neighboring memory cell, and may cause other problems, such as, for example, reducing the useful lifetime of memory cells within an array.
It would be desirable to alleviate or prevent thermal crosstalk between neighboring memory cells of PCM arrays.